# Copyright (c) 2006-2007 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Steve Reinhardt
# 	   Gou Pengfei

import os
import sys
import m5
from m5.objects import *
#m5.AddToPath('../common')

# Define Cache Class
class MyCache(BaseCache):
    assoc = 2
    block_size = 64
    latency = '2ns'
    mshrs = 10
    tgts_per_mshr = 5

# Define CPU, system and Memory Hierarchy
#cpu = InOrderCPU( cpu_id = 0 )
cpu = DerivO3CPU(cpu_id = 0,
		smtFetchPolicy='RoundRobin',
		#smtIQThreshold = 80,
		numThreads=1)
#cpu = TimingSimpleCPU(cpu_id = 0, function_trace = True )
#cpu.addPrivateSplitL1Caches(MyCache(size='256kB'), MyCache(size='256kB'))
cpu.addTwoLevelCacheHierarchy(MyCache(size='256kB'), MyCache(size='256kB'),
                              MyCache(size='2MB'))
cpu.clock = '500MHz'

system = System ( cpu = cpu,
                  physmem = PhysicalMemory(),
                  membus = Bus(),
                  mem_mode = 'timing' )

system.physmem.port = system.membus.port
cpu.connectMemPorts ( system.membus )

root = Root ( system = system )

# Since we're in batch mode, dont allow tcp socket connections
m5.disableAllListeners()

# set default maxtick... script can override
# -1 means run forever
maxtick = m5.MaxTick

process1 = LiveProcess ( cmd = 'test1',
			executable = os.path.join('/export/homeO3/pengfei/ttools2/src/c/simple/dt_stat.gst') )

#process2 = LiveProcess ( cmd = 'test2',
#                        executable = os.path.join('/export/homeO3/pengfei/ttools2/src/c/simple/pow_t.gst') )


# tweak configuration for specific test
root.system.cpu.workload = process1
#root.system.cpu.workload = process1
# instantiate configuration
m5.instantiate(root)

# simulate until program terminates
exit_event = m5.simulate(maxtick)

print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()
